Espressif Systems /ESP32-S3 /EFUSE /RD_REPEAT_DATA1

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Interpret as RD_REPEAT_DATA1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VDD_SPI_DREFM 0VDD_SPI_DREFL 0 (VDD_SPI_XPD)VDD_SPI_XPD 0 (VDD_SPI_TIEH)VDD_SPI_TIEH 0 (VDD_SPI_FORCE)VDD_SPI_FORCE 0 (VDD_SPI_EN_INIT)VDD_SPI_EN_INIT 0 (VDD_SPI_ENCURLIM)VDD_SPI_ENCURLIM 0VDD_SPI_DCURLIM 0VDD_SPI_INIT 0VDD_SPI_DCAP 0WDT_DELAY_SEL 0SPI_BOOT_CRYPT_CNT 0 (SECURE_BOOT_KEY_REVOKE0)SECURE_BOOT_KEY_REVOKE0 0 (SECURE_BOOT_KEY_REVOKE1)SECURE_BOOT_KEY_REVOKE1 0 (SECURE_BOOT_KEY_REVOKE2)SECURE_BOOT_KEY_REVOKE2 0KEY_PURPOSE_0 0KEY_PURPOSE_1

Description

BLOCK0 data register 2.

Fields

VDD_SPI_DREFM

SPI regulator medium voltage reference.

VDD_SPI_DREFL

SPI regulator low voltage reference.

VDD_SPI_XPD

SPI regulator power up signal.

VDD_SPI_TIEH

SPI regulator output is short connected to VDD3P3_RTC_IO.

VDD_SPI_FORCE

Set this bit and force to use the configuration of eFuse to configure VDD_SPI.

VDD_SPI_EN_INIT

Set SPI regulator to 0 to configure init[1:0]=0.

VDD_SPI_ENCURLIM

Set SPI regulator to 1 to enable output current limit.

VDD_SPI_DCURLIM

Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).

VDD_SPI_INIT

Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.

VDD_SPI_DCAP

Prevents SPI regulator from overshoot.

WDT_DELAY_SEL

Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.

SPI_BOOT_CRYPT_CNT

Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.

SECURE_BOOT_KEY_REVOKE0

Set this bit to enable revoking first secure boot key.

SECURE_BOOT_KEY_REVOKE1

Set this bit to enable revoking second secure boot key.

SECURE_BOOT_KEY_REVOKE2

Set this bit to enable revoking third secure boot key.

KEY_PURPOSE_0

Purpose of Key0.

KEY_PURPOSE_1

Purpose of Key1.

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